The present invention is related to systems and methods for power reduction in a semiconductor device.
Semiconductor designs often include a number of pipelined data paths that are exemplified in FIGS. 1a-1b. In particular, a pipelined data path 100 is shown in FIG. 1a, and a timing diagram 101 depicting operation of data path 100 is shown in FIG. 1b. As shown, pipelined data path 100 includes a number of D flip-flops 110 each separated by a combinational logic block 120. Each of D flip-flops 110 is fed by a D input 130 and a clock input 140, and each includes an output 115. In operation, output 115 is changed to reflect input 130 of the respective D flip-flop each time a rising edge of clock input 140 is received.
To operate properly, a preceding output must stabilize and propagate through the intervening combinational logic before the subsequent rising edge of the clock is received at the input of the subsequent flip-flop. As a particular example, output 115a of flip-flop 110a must switch to reflect input 130a (depicted as a value 131) on a rising edge 141 of clock input 140, and output 115a must propagate through combinational logic 120a and stabilize as input 130b (depicted as a value 133) before a subsequent rising edge 143 of clock input 140. Thus, for the design to operate properly, a period 150 of clock input 140 must be greater than a delay time 160 that includes the time to switch the preceding flip-flop, and to propagate through the intervening combinational logic.
Further, where it is desirable to minimize gate count and power dissipation, delay time 160 is designed to be very close to period 150. This approach can be used to minimize the number of pipeline stages, and thus the number of flip-flops used in a particular design. However, such an approach limits operational efficiencies that may be achieved in multi-rate systems. Thus, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for power reductions in semiconductor devices.